Software interrupts, or SVCs as they are now known, are generated by using the ARM instruction SVC. This causes an exception to be taken, and forces the processor into Supervisor mode, which is privileged. A user program can request services from an operating system through such exception handling mechanisms.1
In the AArch64 execution state, there are three privileged modes and one user mode. These are referred to as exception levels. The higher the exception level, the more privilege the code has.
The AArch64 processor provides two major modes of operation, referred to as execution states. They are 32-bit AArch32 state, and 64-bit AArch64 state.
In the A32 and T32 instruction sets, the Program Counter(PC) and Stack Pointer(SP) are general purpose registers. This is not the case in A64 instruction set.
As a general-purpose register in ARMv7, the PC introduced compiler complications and complex pipeline design.
Removing direct access to the PC in ARMv8 makes return prediction easier and simplifies the ABI specification.
ISO/IEC C++ standard basic types specification: Fundamental types, Compound types and CV-qualifiers.
The ISA is a contract between the hardware and the software. It defines the set of instructions and the set of registers that the hardware must support.
The most important components of the CPU are the registers, where data is stored, and the arithmetic and logic unit (ALU), where arithmetic and logical operations are performed on the data.
Arm® processors provide general-purpose and special-purpose registers. Some additional registers are available in privileged execution modes.
Registers which can be used freely are referred to as volatile, and registers which must be preserved or restored before returning are referred to as non-volatile.
How to compile/generate AArch32 code and run on an AArch64 machine?
Linaro empowers rapid product deployment within the dynamic Arm ecosystem.
Arm GNU Toolchain is a community supported pre-built GNU compiler toolchain for Arm based CPUs.
In computer science, a calling convention is an implementation-level (low-level) scheme for how subroutines or functions receive parameters from their caller and how they return a result.
ARM 最初的简称是 Acorn RISC Machine。ARM 使用的内核与指令集并不一一对应。
1990年11月，Acorn、Apple 和 VLSI 共同出资创建了 ARM。Acorn RISC Machine 也正式更名为 Advanced RISC Machine。
ARM11 之后，ARM 处理器内核不再以 ARM 作为前缀。但 ARM 这个单词并没有在 Cortex 系列中消失，Cortex的三大系列 M-R-A，合起来就是 ARM。
有5种指令集最为常见，它们构成了处理器领域的5朵金花。
This article is about the collection of datasheet/textbooks/references on the three major mainstream CPUs.