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  • in c
  • 5 min read

C Named Constants

const-qualified read-only variables must be initialized and named at the same time as they are defined.

Pointers are opaque objects that can remain in a valid, null or indeterminate state. Always initialise pointers to 0 as soon as possible.

  • in c
  • 5 min read

const qualifier in C

const is the abbreviation for "constant". Unfortunately, because of this, many people think that the value qualified by const is a constant. This is not correct. More accurately, it should be a read-only variable whose value cannot be used at compile time because the compiler does not know its stored content at compile time. Perhaps this keyword should have been replaced by readonly. So what is the use and meaning of this keyword?

The original purpose of const was to replace precompiled instructions, eliminating their shortcomings and inheriting their advantages. Let's see the difference between it and the #define macro.

In C, the const keyword should probably be replaced with readonly.

  • in c
  • 9 min read

C Pointer as Function Argument

So far, we've discussed C Pointers and Arrays, C Character Pointer and String Manipulation and C Pointer and Array Cross Reference with Mismatched Type. To be frank, there are some very confusing names for some of these concepts, and it's very easy for even an old hand programmer to get them all mixed up.

In this article, we'll explore the syntax of passing parameters to functions using arrays or pointers. What does it actually do behind the scenes? Can it really pass an array or a pointer to a function? What is the connection and difference between these two ways of passing parameters?

  • in arm
  • 5 min read

ARM64 exclusive Load/Store

ARMv7-A and ARMv8-A architectures both provide support for exclusive memory accesses. In A64, this is the Load/Store exclusive (LDXR/STXR) pair.

In an SMP (Symmetric multiprocessing) system, data accesses must frequently be restricted to one modifier at any particular time.

  • in arm
  • 7 min read

ARM64 One-Way Barriers

In the previous article ARM64 Memory Barriers, we systematically sorted out and summarized common memory barrier instructions.

AArch64 adds new load and store instructions with implicit barrier semantics. These require that all loads and stores before or after the implicit barrier are observed in program order.

  • in arm
  • 11 min read

ARM64 Memory Barriers

On most modern uniprocessors memory operations are not executed in the order specified by the program code. In single threaded programs all operations appear to have been executed in the order specified, with all out-of-order execution hidden to the programmer – however in multi-threaded environments (or when interfacing with other hardware via memory buses) this can lead to problems. To avoid problems, memory barriers can be used in these cases.

  • in arm
  • 5 min read

ARM64内存模型——内存屏障之因

在上一篇 ARM64 Memory Ordering - re-ordering 中，我们介绍了编译器编译时和 CPU 执行时，可能为了提高并行效率，会将指令重排乱序执行。本篇梳理了不同的内存模型下，多处理器并发竞争访问存储器时，指令重排乱序执行可能导致的结果非预期风险。

特别地，在 ARM64 实现的典型的弱一致性内存模型下，程序可能需要添加适当的同步操作来避免竞争访问以保障读写次序。这里说的“同步操作”指的是内存屏障指令，它是系统编程中很重要的一部分，特别是在多核并行编程中。