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  • in arm
  • 6 min read

ARM from ADR to LDR

The pseudo addressing mode instruction LDR allows an immediate data value or the address of a label to be loaded into a register. The ADR instruction forms address of a label at a PC-relative offset.

  • in arm
  • 3 min read

ARM ADRP and ADRL pseudo-instruction

ADRL is similar to the ADR instruction, except ADRL can load a wider range of addresses because it generates two data processing instructions.

  1. In A32, the ADRL pseudo-instruction calculates an offset using two separate ADD or SUB operations.
  2. In A64, on the other hand, ADRL assembles to two instructions, an ADRP followed by an ADD.
  • in arm
  • 5 min read

ARM ADR (PC-relative)

The ADR instruction forms address of a label at a PC-relative offset.

It loads an address within a certain range, without performing a data load.

  • in arm
  • 7 min read

ARM LDR literal and pseudo-instruction

The AArch64 architecture is a classic example of a load-store architecture.

There are three fundamental addressing modes in AArch64 instructions: register offset, immediate offset, and literal.

The LDR instruction is either an ordinary memory access instruction or a pseudo-instruction that loads an address in a large range. When its second parameter is preceded by "=", it represents a pseudo-instruction.

The pseudo addressing mode allows an immediate data value or the address of a label to be loaded into a register, and may result in the assembler generating more than one instruction.

  • Literal: label
  • Pseudo load: =<immediate|symbol>
  • in arm
  • 3 min read

ARM pseudo-instructions

Instructions and pseudo-instructions make up the code a processor uses to perform tasks.

Directives are commands issued to the assembler, which are processed by the assembler during source program assembly. Pseudo-instructions can complete functions such as selecting the processor, defining the program mode, defining data, allocating storage areas, and indicating the end of the program. In short, pseudo-instructions can be broken down into sets of several instructions.

  • in arm
  • 8 min read

ARM64 System calls

Software interrupts, or SVCs as they are now known, are generated by using the ARM instruction SVC. This causes an exception to be taken, and forces the processor into Supervisor mode, which is privileged. A user program can request services from an operating system through such exception handling mechanisms.1

  • in arm
  • 5 min read

ARM64 Execution States

The AArch64 processor provides two major modes of operation, referred to as execution states. They are 32-bit AArch32 state, and 64-bit AArch64 state.