ADRL is similar to the ADR instruction, except ADRL can load a wider range of addresses because it generates two data processing instructions.
ADRL pseudo-instruction calculates an offset using two separate ADD or SUB operations.ADRL assembles to two instructions, an ADRP followed by an ADD.The ADR instruction forms address of a label at a PC-relative offset.
It loads an address within a certain range, without performing a data load.
In the previous article, we've combed AMR LDR PC-relative and Pseudo instruction to load a value or address to a register.
Here we collect some enlightening demos from some classic textbooks to consolidate knowledge that is not solid.
The AArch64 architecture is a classic example of a load-store architecture.
There are three fundamental addressing modes in AArch64 instructions: register offset, immediate offset, and literal.
The LDR instruction is either an ordinary memory access instruction or a pseudo-instruction that loads an address in a large range. When its second parameter is preceded by "=", it represents a pseudo-instruction.
The pseudo addressing mode allows an immediate data value or the address of a label to be loaded into a register, and may result in the assembler generating more than one instruction.
label=<immediate|symbol>Instructions and pseudo-instructions make up the code a processor uses to perform tasks.
Directives are commands issued to the assembler, which are processed by the assembler during source program assembly. Pseudo-instructions can complete functions such as selecting the processor, defining the program mode, defining data, allocating storage areas, and indicating the end of the program. In short, pseudo-instructions can be broken down into sets of several instructions.
Software interrupts, or SVCs as they are now known, are generated by using the ARM instruction SVC. This causes an exception to be taken, and forces the processor into Supervisor mode, which is privileged. A user program can request services from an operating system through such exception handling mechanisms.1
In the AArch64 execution state, there are three privileged modes and one user mode. These are referred to as exception levels. The higher the exception level, the more privilege the code has.
The AArch64 processor provides two major modes of operation, referred to as execution states. They are 32-bit AArch32 state, and 64-bit AArch64 state.
In the A32 and T32 instruction sets, the Program Counter(PC) and Stack Pointer(SP) are general purpose registers. This is not the case in A64 instruction set.
As a general-purpose register in ARMv7, the PC introduced compiler complications and complex pipeline design.
Removing direct access to the PC in ARMv8 makes return prediction easier and simplifies the ABI specification.
The ISA is a contract between the hardware and the software. It defines the set of instructions and the set of registers that the hardware must support.
The most important components of the CPU are the registers, where data is stored, and the arithmetic and logic unit (ALU), where arithmetic and logical operations are performed on the data.
Arm® processors provide general-purpose and special-purpose registers. Some additional registers are available in privileged execution modes.
Registers which can be used freely are referred to as volatile, and registers which must be preserved or restored before returning are referred to as non-volatile.