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arm#

  • in arm
  • 5 min read

ARM64 exclusive Load/Store

ARMv7-A and ARMv8-A architectures both provide support for exclusive memory accesses. In A64, this is the Load/Store exclusive (LDXR/STXR) pair.

In an SMP (Symmetric multiprocessing) system, data accesses must frequently be restricted to one modifier at any particular time.

  • in arm
  • 7 min read

ARM64 One-Way Barriers

In the previous article ARM64 Memory Barriers, we systematically sorted out and summarized common memory barrier instructions.

AArch64 adds new load and store instructions with implicit barrier semantics. These require that all loads and stores before or after the implicit barrier are observed in program order.

  • in arm
  • 11 min read

ARM64 Memory Barriers

On most modern uniprocessors memory operations are not executed in the order specified by the program code. In single threaded programs all operations appear to have been executed in the order specified, with all out-of-order execution hidden to the programmer – however in multi-threaded environments (or when interfacing with other hardware via memory buses) this can lead to problems. To avoid problems, memory barriers can be used in these cases.

  • in arm
  • 5 min read

ARM64内存模型——内存屏障之因

在上一篇 ARM64 Memory Ordering - re-ordering 中，我们介绍了编译器编译时和 CPU 执行时，可能为了提高并行效率，会将指令重排乱序执行。本篇梳理了不同的内存模型下，多处理器并发竞争访问存储器时，指令重排乱序执行可能导致的结果非预期风险。

特别地，在 ARM64 实现的典型的弱一致性内存模型下，程序可能需要添加适当的同步操作来避免竞争访问以保障读写次序。这里说的“同步操作”指的是内存屏障指令，它是系统编程中很重要的一部分，特别是在多核并行编程中。

  • in arm
  • 6 min read

ARM64 Memory Types

The ARMv8 architecture defines two mutually-exclusive memory types. All regions of memory are configured as one or the other of these two types, which are Normal and Device. A third memory type, Strongly Ordered, is part of the ARMv7 architecture. The differences between this type and Device memory are few and it is therefore now omitted in ARMv8.

In addition to the memory type, attributes also provide control over cacheability, shareability, access, and execution permissions. Shareable and cache properties pertain only to Normal memory. Device regions are always deemed to be non-cacheable and outer-shareable. For cacheable locations, you can use attributes to indicate cache allocation policy to the processor.

  • in arm
  • 7 min read

ARM64 Memory Ordering

Early implementations of the ARM architecture such as the ARM7TDMI executed all instructions in program order. Each instruction was fully executed before the next instruction was started.

Newer processors employ a number of optimizations that relate to the order in which instructions are executed and the way memory accesses are performed.

  • in c, arm
  • 11 min read

C Pointer Explanation in armasm

A C program, whatever its size, consists of functions and variables. A function contains statements that specify the computing operations to be done, and variables store values used during the computation.

Every time we want to use a variable(e.g. char c; int i;), we must declare it in advance, which actually allocates a space in memory with the width corresponding to the variable type.

A pointer is a variable that contains the address of another variable.