In this article, we'll comb through the Load/Store addressing modes based on offset and index in ARM(A32/A64).
There are three fundamental addressing modes in AArch64 instructions: register offset, immediate offset, and literal.
For information about addressing modes, see Load/Store addressing modes.
In linux arm64 kernel, the transition of the PC from the physical address space to the real virtual address space is completed with the last three instructions of head.S after MMU enabled.
Since both the LDR pseudo-instruction and the ADRP instruction can load the address of a label, and the LDR pseudo-instruction can address the 64-bit address space, and the addressing range of the ADRP instruction is the current PC address ±4GB, then what is the necessity of having an ADRP instruction when there's already an LDR pseudo-instruction?
The pseudo addressing mode instruction LDR allows an immediate data value or the address of a label to be loaded into a register. The ADR instruction forms address of a label at a PC-relative offset.
In the previous two articles(ARM ADR (PC-relative) & ARM ADRP and ADRL pseudo-instruction), we've combed AMR ADR instructions to load a pc-relative label address to a register.
Here we collect some enlightening demos from some classic textbooks to consolidate knowledge that is not solid.
ADRL is similar to the ADR instruction, except ADRL can load a wider range of addresses because it generates two data processing instructions.
ADRL pseudo-instruction calculates an offset using two separate ADD or SUB operations.ADRL assembles to two instructions, an ADRP followed by an ADD.The ADR instruction forms address of a label at a PC-relative offset.
It loads an address within a certain range, without performing a data load.
In the previous article, we've combed AMR LDR PC-relative and Pseudo instruction to load a value or address to a register.
Here we collect some enlightening demos from some classic textbooks to consolidate knowledge that is not solid.
The AArch64 architecture is a classic example of a load-store architecture.
There are three fundamental addressing modes in AArch64 instructions: register offset, immediate offset, and literal.
The LDR instruction is either an ordinary memory access instruction or a pseudo-instruction that loads an address in a large range. When its second parameter is preceded by "=", it represents a pseudo-instruction.
The pseudo addressing mode allows an immediate data value or the address of a label to be loaded into a register, and may result in the assembler generating more than one instruction.
label=<immediate|symbol>Instructions and pseudo-instructions make up the code a processor uses to perform tasks.
Directives are commands issued to the assembler, which are processed by the assembler during source program assembly. Pseudo-instructions can complete functions such as selecting the processor, defining the program mode, defining data, allocating storage areas, and indicating the end of the program. In short, pseudo-instructions can be broken down into sets of several instructions.